Life after DFM

For the past couple of years, the Design Automation Conference (DAC) has been awash in vendors touting their software as design for manufacturing (DFM) tools. Although Gary Smith, Gartner's EDA analyst, says most of the brouhaha is just "design for marketing," the fact that so many vendors are leaping into the fray emphasizes that their customers take the DFM concept very seriously indeed.

And well they should. According to some analysts, DFM could be a harbinger of a time when it will no longer be practical for any but the largest firms to custom-design their chips directly into silicon. Instead, in the post-DFM world, it may be more economical for many electronics firms to employ standard chips with programmable logic for any application that can't drive huge chip volumes. If so, DFM could ultimately mean the end of custom chip design work targeting state-of-the-art manufacturing processes.

In its broadest sense, DFM implies merging the design and manufacturing process. This has enormous implications for chip makers, according to Mike Fazeli, manager of EDA strategies at Texas Instruments. "We see a lot of challenges connected with DFM, including different interfaces and protocols and entirely new kinds of tools," Fazeli says.

Meeting these challenges will not come cheap. DFM will force design teams to address the peculiarities of the target manufacturing process and draw manufacturing engineers into increasingly arcane design issues. What was, before DFM, a simple series of logical steps will become, post-DFM, a complex iterative process of communication between groups with different skill sets and disciplines.

"With DFM the design rules will number in the thousands, or tens of thousands, rather than in today's hundreds," says Franklin Kalk, research fellow at DuPont Photomasks.

Although the net effect of DFM may be "better, faster, cheaper" chips down the line, it will add complexity and expense to all stages of the process of preparing a chip to be manufactured. "We're moving into an era in which there will need to be a great deal of interaction between designers and manufacturers at all levels, meaning a huge collaboration effort to implement a realistic DFM strategy," says Chuck Byers, director of brand management at TSMC.

Because the need for collaboration between design and manufacturing will increase with each successive node, the high cost of bringing a chip into production will continue to increase as well. And that's a tad ominous, considering that custom chip design is becoming a beleaguered business model without the help of DFM, according to Jim Tully, vice president and chief of research at the market research firm Gartner.

"The cost of designing a custom chip at the smaller geometries has slipped outside the financial reach of smaller electronics firms," Tully says. As that trend continues, the cost of designing a state-of-the-art chip could balloon to as high as $100 million by 2010—a sum far beyond the means of many established medium-size firms, let alone a startup (see the "Cost of design for an 8-million-gate PDA SoC" graphic). Given the up-front expense, such chips are economical only when they're to be manufactured in huge volumes. "As a result, we expect far fewer designs at those nodes," Tully says.

The need for each design to drive big numbers complicates another important financial trend: the increasing cost of building a fab. By 2010 chip makers will need to recover capital investment costs approaching $5 billion. With ballooning design costs reducing the overall number of designs, each design that actually goes into production will need to achieve even higher volumes than might otherwise be the case.

This overwhelming incentive for greater volumes will force designers and manufacturers in the post-DFM world to make chips that are usable for multiple applications. "The ideal business model will be to make general-purpose chips that can be reconfigured as needed," says Tully.

Although Tully says he believes that there will still be some fully-custom single-application work at the newest nodes, he sees the bulk of chips made at the smaller geometries including programmable logic to extend their useful lifetime and thereby increase overall manufacturing volumes.

"Fewer companies will look to custom design of 'hardwired' circuitry to create a competitive advantage," Tully says. "Instead, they'll figure out how to reconfigure and reuse a fairly standard set of chips to do new and innovative things."

That's a scenario that the programmable logic chip firms are expecting to develop, according to Ronnie Vasishta, vice president of technology marketing for LSI Logic.

"What we've tried to do is build automation into our products so designers don't have to worry about the complexities of manufacturing, such as RET and, in the future, DFM," Vasishta says.

What emerges is a semiconductor industry that's very different from that of today. Rather than numerous fabs manufacturing numerous designs at the newest nodes, there will be far fewer fabs—perhaps only two or three—manufacturing a very small number of designs but in enormous volumes. And rather than designing innovation directly into the silicon, the design firms of the future will work at a higher level.

"The emphasis will shift to system design tools that allow designers to add value at either the software level or at the programmable logic level of the chip," Tully says. "Designers will need to be more concerned with reconfiguration than just with optimizing silicon."

This post-DFM scenario is reinforced by the demographics of the design engineering community, according to Wally Rhines, chairman and CEO of Mentor Graphics. "There isn't likely to be sharp growth in the number of trained design engineers, so the industry will need FPGA technology simply to increase engineer productivity enough to cope with the added complexity of electronics products in future years," he says. "There will be fewer fabs making digital chips, and those fabs will be more commodity-like, with more designs utilizing FPGA circuitry."

Not everyone agrees that the future lies in general-purpose chips. Gary Smith, the Gartner analyst who covers EDA, points out that the issue isn't so much the need for greater volume but the need for greater value.

"The thinking is that consumers will drive most of the IC spending in the future and that they will spend $5 for an IC," he says. "But with the introduction of the SoC, the IC is almost all of the system, so you must compare system cost with SoC cost, rather than comparing a $5 'component' with an SoC—an apples-and-oranges comparison." In other words, it may still be economical to custom-design specialized chips in smaller volumes, providing that those chips perform enough valuable functions to command a high price. "The Intel microprocessor has been an SoC for a while now, and it does not sell for $5," Smith points out.

However, Ted Vucurevich, chief technology officer at Cadence Design Systems, points out that SoC designs are themselves a vehicle for chip reusability. "SoCs needn't be designed for a single application use," he says. "SoC programmability at the software level will make it possible to spread the payback for a chip design over a longer period of years." Some analysts even envision "universal" SoCs that have multiple copies of many different types of IP, which software and firmware programmers can choose to activate (or leave quiescent) at will. "If current trends continue and the cost of design becomes staggeringly high, we may eventually get to a stage where it makes more sense to make one large batch of chips where you don't use all the functionality that's inside," says Klaus Rinnen, a semiconductor analyst at Gartner.

Others question whether state-of-the-art fabs will be as rare as Tully seems to think. Industry analyst Boris Petrov, of the Petrov Group, for example, believes that alliances and consortia will allow smaller players to participate in the building of newer fabs, citing the successful example of IBM, AMD and Chartered, all of which have been involved in partnerships to share fab-building expenses. "In such alliances, each partner has a very different agenda and its own needs, yet their cooperation is genuine and very substantial," he says. Having more fabs at the newer nodes would presumably create more competition, driving the cost of manufacturing down and making it more economical for smaller firms to continue to do custom design work.

Similarly, 50-year industry veteran Fred Zieber, of Pathfinder Research, believes that the semiconductor industry will figure out a way to make the smaller geometries more efficient and hence more cost-effective.

Economic incentive needed

"I have to believe that a $250 billion industry will figure out some way around these problems," Zieber says. He admits, however, that high design costs may eventually scuttle the economic incentive to do custom design work at the smallest nodes: "There's going to be some point where smaller dimensions don't pay off any longer."

Vucurevich says he thinks foundries may still be able to attract custom designs from smaller firms by combining designs from multiple companies onto a single wafer. "The foundries need to start thinking of a manufacturing run as being more like a shuttle bus than a passenger car," he says. "Getting multiple companies to coordinate their designs to take advantage of economies of scale is a relatively simply supply chain problem."

Breakthroughs in process technology could also make custom design more viable at the newest nodes, according to Rich Wawrzyniak, an analyst at Semico Research. "Employing nanotech in chip manufacturing might make nonphotographic processes more efficient," he says, "making it easier to design chips at an acceptable yield without the extra overhead of DFM."

However, some analysts are even more pessimistic than Tully when it comes to the long-term future. Dr. Robert Castellano, of The Information Network, for example, believes that the increasing expense of design could be a harbinger of the collapse of Moore's Law as the economic basis of the semiconductor industry.

"We may just really reach a point where its more cost-effective to stop making chip components smaller but instead make them a bit bigger but cheaper to manufacture," he says.

Similarly Risto Puhakka, president of VLSI Research, sees a future in which the industry may need to move beyond the silicon-based product model. "What's very clear is that the classical CMOS is starting to see its end of life," he says.

Although the DFM-driven doomsday may still be years away, the mere fact that DFM remains on the agenda argues that the fundamental relationship between design and manufacturing is changing. And if that change greatly increases the cost of preparing a chip to be manufactured, then it's inevitable that electronics firms will be looking for ways to save money, even if that means throwing the concept of custom design work onto the scrap heap of high-tech history.